The present invention relates to semiconductor devices, and particularly to isolating semiconductor fins from a substrate.
It is becoming increasing common to fabricate devices that include three-dimensional topographical features such as fins. Once such device is a fin field effect transistor (finFET), which may provide solutions to field effect transistor (FET) scaling problems that may occur at, and below, the 22 nm node. FinFET structures include at least one narrow semiconductor fin, a source region located on one end of the semiconductor fin, and a drain region located on the opposite end of the semiconductor fin. The fin may gated on at least two sides of each of the semiconductor fin between the source region and the drain region. By applying a voltage to the gate, the conductivity of the fin may be changed to allow current to flow from the source region to the drain region.
In order to electrically isolate the finFET from the underlying substrate, finFETs may typically be fabricated from a semiconductor-on-insulator (SOI) substrate, where the semiconductor fin may be separated from a base substrate by a buried insulator layer. FinFETs may also be fabricated from bulk substrates to reduce wafer cost and/or enable formation of certain devices in the bulk substrate. However, the fins of finFETs fabricated from bulk substrates are typically not electrically isolated from the substrate, potentially resulting in reduced device performance. Therefore, a method of fabricating finFETs from a bulk substrate so that the fins are electrically isolated from the bulk substrate may, among other things, be desirable.